Three operations namely right turn, left turn, and hazard have
been simulated and confirmed to work correctly. The simulation
output is attached in the section 2.1.1 of Appendix.
The following problems were found during the lab:
Although the description of ``default transition'' is allowed
in the state machine in PLDshell, there has to be at least one
explicit transition for each state. Therefore a transition for a
state which always takes place must be written like
l3 := VCC -> neutral
It seems to be unsophisticated a little bit. Especially, having
VCC, which is circuit level abstract, in the state machine
description which is logic level abstract should be avoided.
The chip part number 85C224 could not accommodate my design.
Hence the chip-independent part INTEL_ARCH was used.
