Lab 9: Sequence Detector

Title           Lab9
Pattern         pds
Revision        1       
Author          Hitoshi Oi
All Rights Reserved
Company         Univ of South Florida
Date            11/17/95

CHIP  lab9  85C224

; pin assignments

PIN     CLK     ; clock pin
PIN     IN      ; Input
PIN     Q0      ; LSB
PIN     Q1
PIN     Q2      ; MSB
PIN     OUT     ; Output

; Boolean equations for registers

EQUATIONS
      
	OUT = Q2
	Q0.CLKF = CLK
	Q1.CLKF = CLK
	Q2.CLKF = CLK

STATE
MOORE_MACHINE
DEFAULT_BRANCH S0
; State Assignment
	S0 = /Q0 * /Q1 * /Q2
	S1 = Q0 * /Q1 * /Q2
	S2 = /Q0 * Q1 * /Q2
	S3 = Q0 * Q1 * /Q2
	S4 = /Q0 * /Q1 * Q2

; State Transition
	S0 := ZERO -> S1
	S1 := ZERO -> S2
	S2 := ZERO -> S3
	S3 := ZERO -> S4
	S4 := ZERO -> S4

CONDITIONS        
     ZERO = /IN
SIMULATION

; set up vector and trace
; set to known state, preload registers (all low)

VECTOR ZEROS := [ Q2, Q1, Q0 ]
TRACE_ON  IN CLK  Q2  Q1  Q0  OUT
SETF  /IN  /CLK
PRLDF  /Q0  /Q1  /Q2        ; clock set before
				; preload command
SETF /IN                
CLOCKF CLK              ;0
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
FOR I := 0 to 1
	DO
	BEGIN
	CLOCKF CLK
	END
		;Two 0's
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
FOR I := 0 to 2
	DO
	BEGIN
	CLOCKF CLK
	END
		;Three 0's
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
FOR I := 0 to 3
	DO
	BEGIN
	CLOCKF CLK
	END
		;Four 0's
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
FOR I := 0 to 4
	DO
	BEGIN
	CLOCKF CLK
	END
		;Five 0's
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
FOR I := 0 to 9
	DO
	BEGIN
	CLOCKF CLK
	END
		;Ten 0's
SETF IN                 
CLOCKF CLK              ;1
CLOCKF CLK              ;1
SETF /IN                
CLOCKF CLK              ;0
SETF IN                 
CLOCKF CLK              ;1
SETF /IN                
CLOCKF CLK              ;0
CLOCKF CLK              ;0
TRACE_OFF

; end of simulation