In this report, five technology mapping algorithms were introduced. Two were classical and standard, and three were recently presented. There are many other algorithm such as [5], [6], [10], that could not be included in this report. IEEE Transactions on Computer-Aided Design, International Conference on Computer-Aided Design, and IEEE/ACM Design Automation Conference would be good information sources for this topic. There are some criterion for designing technology mapping algorithms: LUT number minimization (utilization of LUT's on a FPGA), delay minimization, routability, execution time and memory usage. Recent algorithms combines technology mapping with other tasks, such as placement or routing, to improved the over all performance of the final circuit. All the algorithm introduced here used Xilinx 3000 series FPGA for their experiments. This is because, even the latest one ( m.map) experiments are thought to have been done three or more years ago. It is expected that there appear new algorithms soon that take into account the features of Xilinx 4000 series of which CLB is much more powerful than that of 3000 series. The progress of semiconductor process technology makes more CLB's and interconnection resources available on a FPGA chip. Faster and more efficient algorithms will be needed to fully utilize these resources.
