Since this traffic light controller has five states (
), they were
coded into 3-bit numbers as shown in Figure 0.1.
According to the state transition diagram and state numbers,
first, output signals for each light (green, yellow, and red) for
both highway and farm-road are generated:
Next, signals to reset 30-seconds and 5-seconds timers
(in other words, when these signals are 0, timers start counting
the period) generated as follows:
The last group of signals are to set Flip-Flops of the state-machine. Note bn corresponds to the n-th bit of the state number.
The schematic of the traffic light controller is shown in Figure 0.2. The sensor on the farm-road is simulated by a DIP switch. The system is initialized by ``reset'' push-button on the FPGA board. System clock is generated by dividing the 15Hz output of the OSC4 block, by 8 (3-bit counter). If we had to follow the specification, this design would be incorrect. However:
If absolute and precise timing is need, we should have used a crystal oscillator. Hence this design seems to be sufficient. Two 7-segments LED displays are added to monitor the operations of the state-machine and the 5-seconds timer.
Figure: Traffic Controller Schematic
