A T-flip-flop (FF) changes its state value at each falling edge (transition from 1 to 0) of the clock signal. By connecting T-FF in a cascade manner we can configure a binary ripple carry counter of arbitrary number of bits. Figure 0.1 shows the timing diagram of the lowest four bits of the ripple adder (see Figure 0.3 for signal names).
The transition from 1 to 0 of clock input triggers the transition of the next stage, hence this configuration of a counter is called a ripple counter.
